The integration of an N-channel MOS component by using a dielectrically insulated well formed from a SOI (Silicon On Insulator) substrate is well known. Particularly, the SOI substrate defines a vertical dielectric insulation, whereon convenient dielectric trenches are formed, effective to define a side dielectric insulation, thus forming a dielectrically insulated well. With reference to FIGS. 1A and 1B an integrated structure 11 forming an N-channel MOS or NMOS component in a dielectrically insulated well is described hereafter. Particularly, FIGS. 1A and 1B represent the layout and the cross section of the integrated structure 11 respectively.
The integrated structure 11 includes a substrate 1 of a first dopant type, particularly of the N type, whereon a buried oxide layer 2 is formed, which forms the vertical dielectric insulation of a dielectrically insulated well 3 of a second dopant type, particularly of the P type. Particularly, the dielectrically insulated well 3 is formed in a silicon layer 4, defined as silicon on-insulator or SOI of the first N-dopant type through dielectric trenches 5 forming the side dielectric insulation of the well 3.
Dielectric trenches 5 can be formed conventionally by using for example dielectric walls 12 filled in with a convenient filler 13, for example polycrystalline silicon. The dielectrically insulated well 3 is a P-region and it is the bulk region of the NMOS component formed in the integrated structure 11. Respective N-regions 6A and 6B are provided in this dielectrically insulated well 3, which are effective to form the NMOS component drain and source regions, and thereon a structure effective to form the NMOS component gate terminal is provided in correspondence with a gate region 7. The NMOS component is thus completed by growing a thick oxide 8 delimiting NMOS component active areas, and depositing a surface dielectric 9 covering the thick oxide 8 and the gate structure, as well as finally depositing a metallization 10.
The substrate 1 serves as mechanical support during the NMOS component manufacturing steps. It is worth noting that the dielectrically insulated well 3, forming the bulk region of the P-type wherein the NMOS component is integrated, is thus completely dielectric-surrounded, particularly the buried oxide 2 and dielectric trenches 5. In practice, an excess of positive charge in dielectric regions 2 and 5 surrounding the NMOS component dielectrically insulated well 3 (with respect to a commonly accepted value) lets preferred bulk or side conduction channels to be formed along the walls of dielectric trenches 5, schematically indicated with arrows F in FIG. 1B. These preferred conduction channels can be electrically detected as undesired leakage currents being present between the NMOS component source and drain regions, independently from the bias value and type (positive or negative) of the gate region 7. It is worth noting that these excessive positive charges can be inserted in the dielectric during the working steps or stocked therein during ionizing radiation exposure periods, as it happens for example with devices for nuclear or space applications.
The traditional integrated structure 11 effective to form an NMOS component in a dielectrically insulated well 3 is thus intrinsically subject to the formation of parasitic elements, particularly the preferred conduction channels in the dielectrically insulated well 3, of the NMOS type as well. The formation of these preferred NMOS parasitic channels and related undesired leakage currents is known to be eliminated by integrating around the NMOS component a heavily P-doped surface layer, the so-called guard-ring. Particularly, as schematically shown in FIGS. 2A and 2B, an integrated structure 20 effective to form such an NMOS component comprises, in contact with the NMOS component dielectrically insulated well 3, a ring cut-off region 14 located between dielectric trenches 5 and regions 6A and 6B, as well as a further thick oxide area 15 grown between the ring cut-off region 14 and the drain and source regions 6A and 6B. FIGS. 2A and 2B represent the layout and the cross section of the integrated structure 20 respectively. The ring cut-off region 14 is a heavily-doped region effective to cut off the formation of surface or bulk channels, near the interface between the well 3 and the dielectrically insulated regions 6A and 6B.
This first known approach, though advantageous for the cut-off of possible NMOS parasitic channels, involves however greater dimensions in terms of integration area. In fact, for a correct electric operation of the NMOS component formed via the integrated structure 20, the ring cut-off region 14 must be kept at a minimum distance from the drain region 6A. This minimum distance is particularly a function of the nominal breakdown voltage required for the NMOS component. It is also worth noting that the ring cut-off region 14, besides being heavily doped, must be formed so as not to be excessively diffused in order to reduce the overall occupation area of the NMOS component formed by the integrated structure 20.
The parameters indicated, i.e. the heavy doping and the reduced diffusion required for the ring cut-off region 14, constrain the integration of this region 14 in a final step of the process sequence for integrating the structure 20, particularly after the gate polysilicon layer integration step, to limit the thermal cycles undergone by this region 14. This involves also gate structure layout constraints, such as for example the contact region definition or the contact resistance minimization. Finally, the implementation of the ring cut-off region 14 in dielectrically insulated wells 3, besides the integration area increase, involves also the change in traditional integration architectures, mainly when integrating high integration density circuits, such as CMOS logic circuits.
Drain and source regions 6A and 6B are also known to be spaced from the thick oxide 8 delimiting the active area, as in the integrated structure 30 schematically shown in FIGS. 3A and 3B which represent the layout and the cross section of the integrated structure 30 respectively. In the NMOS component active area formed by via the integrated structure 30, the thick oxide 8 and the drain and source regions 6A and 6B are thus separated by a dielectric region 16 whose oxide thickness, commonly indicated as VAPOX, is thinner than the thickness of the whole dielectrically insulated well 3 composed of the so-called LOCS and VAPOX oxides.
The integrated structure 30 prevents thus surface channels from being formed between the drain and source regions 6A and 6B outside the gate region 7, which are generated by the positive charge trapping phenomenon in the thick oxide 8. This is for example the case when an NMOS component undergoes a ionizing radiation. In fact it is worth remembering that the ionizing radiation on a semiconductor device causes the formation of electron-hole couples in the whole device volume undergoing the radiation. Particularly, the holes (being positive charges), differently from electrons, are trapped in oxide layers and they can produce an image charge on silicon layers forming subsequently surface channels and leakage. Since the amount of charge trapped is exponentially proportional to the thickness of the oxide layer containing it, this phenomenon is very relevant near the so-called LOCO oxidation regions which are thus particularly sensitive to this effect.
The integrated structure 30 conventionally formed by spacing drain and source regions 6A and 6B is structurally less effective than an integrated structure 20 comprising a ring cut-off region 14. Moreover, such a structure is not very effective in terms of integration area occupation.
The thickness of the dielectric affected by the leakage phenomenon is also known to be reduced by integrating, on the active area, polysilicon or metallization regions, conveniently biased so as to cut off or anyway not favor the surface channel formation. However such approaches damage the so-formed NMOS component occupation area and they also involve structural constraints linked to the polysilicon or metallization region integration with respect to the junctions or edge structures allowing the so-integrated NMOS component voltage seal.
The technical problem underlying the present invention is the provision of an integrated structure effective to form a NMOS component in a dielectrically insulated well having such structural and functional characteristics as to overcome the limits and drawbacks still affecting prior art integrated structures.